TO THE EUROPEAN
PROJECT MARISE WEB SITE
Work Performed & Achievements
During the second year, MARISE project made quite good progress, following closely the original Work Plan. In particular one can notice the successful achievements of AlInAs/InGaAs APDs with record characteristics as needed for applications demonstrators. Significant progress was also made in mastering InGaAsN/AlGaAs material system with low dark current. A summary of these achievements is given hereafter:
Work Package 1: Concepts & Materials
In this WP, three activities are carried out: the first one is dealing with AlInAs/InGaAs material system. Following 10Gb/s APD optimisation during the first year of the project, during this second year material development was oriented towards optimisation of the 40Gb/s vertical APD structure. A series of APD epi-wafers with very thin multiplication layers were grown and delivered with several doping levels of the charge layer. In parallel, a first waveguide UTC structure made on Semi-Insulating InP was fabricated to assess optical device characteristics (refractive indices of the multimode waveguide, propagation losses,...) on dedicated photodiodes test structures. Finally, a first 40Gb/s waveguide APD structure was grown for AlInAs avalanche properties assessment on thick InGaAsP/InP optical waveguide. Concerning SPADs, a series of avalanche structures were grown to investigate APD noise characteristics.
A second activity is dealing with very promising AlGaAs/GaInAsN APD structures made on GaAs substrate. The optimum aluminium content in AlGaAs being optimised during the first year of the project for low noise operation, a major focus on GaInAsN material growth optimisation was conducted although able to absorb 1.3µm wavelength. Besides, adequate ex-situ post-growth annealing to reduce mid-gap semiconductor defects an important progress was made during this second year in improving the growth equipment to minimise water/oxygen contamination resulting in good as-grown InGaAsN material quality. Finally, various AlGaAs/InGaAsN band-gap grading structures were designed and tested, so as to provide critical inputs for the final design of the complete SAGM APD structure.
Work Package 2: Design & Processing
Several achievements are worth noting in this WP; first the achievement of a first generation of AlInAs/InGaAs APDs for 10Gb/s burst mode Rx and SPADs. These APDs exhibit excellent characteristics with a total dark current of 8.3nA at M=10 (a multiplied dark current IdM of 0.1nA was demonstrated which is to our knowledge the lowest ever reported for AlInAs/InGaAs APDs). In addition, an excess noise factor F(M=10)=3.3 and a gain-bandwidth product of 150-160GHz were achieved. All these characteristics allow achieving MARISE objective 1 and place these APDs over the current state of the art.
In a second activity, related to waveguide APDs, a multimode waveguide suitable to achieve high quantum efficiency using lateral illumination was simulated and UTC photodiodes test structures were fabricated using a full 2-inch processing that uses on-wafer anti-reflection coating of ICP dry etched mirror facets. A high responsivity of 0.8A/W and a low TE/TM polarisation dependence loss of 0.1dB were demonstrated on a 25µm length diode. These achievements opened the door for the final fabrication of a waveguide APD. In parallel, AlInAs APDs with a 0.1µm thin avalanche layer were demonstrated with a record gain-bandwidth product of 240GHz.
A third activity is dealing with the fabrication of advanced AlGaAs/InGaAsN APDs. On GaAs substrate, as-grown GaInAsN p-i-n diodes with low residual doping demonstrated on 30µm diameter devices dark currents <1nA at 150kV/cm that meet MARISE target. In addition, the critical grading layer inserted between AlGaAs and InGaAsN was investigated. Both a thin GaAs and a gradual AlGaAs layers have been used and a low carrier trapping at the interface demonstrated.
Work Package 3: Characterisation & Assessment
This work package is devoted to the evaluation of the reliability of the MARISE APDs. The first activity concerns the characterisation of the devices for tasks 1, 2 and 3.2. The interlab comparison initiated during the previous period has been completed during this year. The cross-assessment has been focussed on DC parameters, frequency response and noise measurements. This cross-assessment activity shows the good agreement in the measurements between the 3 sites: USFD, ATL and ADV.
The second activity involves the optimisation of the passivation layer. 2 deposition techniques have been compared: PECVD and ICPCVD on 10 Gb/s AlInAs/InGaAs APDs. SiNx PECVD layer proves out to be the most appropriate technique for passivating these photodiodes with planar junction.
The third activity concerns the lifetest of AlInAs/InGaAs APDs which are driven at 50µA with an in-situ monitoring of the photodiode voltage Vbr. 3 APD runs have first been lifetested during 1500h at 175°C. The MARISE APDs show drifts in Vbr which decreases during ageing time. Dark current and gain are not affected. The third APD generation has been lifetested at two other temperatures namely 125°C and 150°C to see the temperature influence and for activation energy calculation. The activation energy in Vbr is 0.57eV for a drift criteria for 10% in Vbr with a Mean Time To Failure (MTTF) of 55 years for an operating temperature of 50°C.
Work Package 4: Applications
In this WP, two activities made progress during the second year of MARISE: the first activity deals with single photon photoreceivers for applications such as cryptography and OTDR. Three new APD structures have been tested in avalanche and Geiger mode with a demonstration of a decrease of the thermal generation rate by more than a decade at low temperatures compared to the previous generation of APDs. For the final demonstration in free running and gated modes operations, a photoreceiver plat-form has been designed using existing CMOS ASIC and assembled.
The second activity conducted by IMEC is about 10Gb/s burst-mode APD-TIA module and the 40Gb/s APD based TIA chip design. Firstly, the 10G BM-TIA IC design was finalised. Due to lack of STMicroelectronics multi-project-wafer run in 0.25um SiGe BiCMOS technology the milestone M4.2 was delayed. Secondly, the 40Gb/s BM-TIA was specified. The first test chip was designed and under fabrication in the IHP 0.13um SiGe technology. A 40Gb/s APD based TIA IC is currently being designed.